– Siemens Digital Industries Software program, a unit of Siemens AG, on Monday mentioned it launched new software program referred to as Tessent Multi-die that automates a design course of for testing chips made with superior packaging.
Whereas chips have historically been packaged with one silicon tile inside, because the trade faces challenges making options on these tiles smaller and smaller to cram extra computing energy into them, corporations together with Intel are beginning to stack a number of of them, typically mixing and matching completely different applied sciences, to enhance efficiency.
However testing these chips after they're made has been troublesome as there are a number of layers of tiles, and Siemens’ head of the Tessent enterprise Ankur Gupta mentioned till now Siemens has needed to work with prospects on a case-by-case foundation.
Testing is a key a part of the chip-making course of and a port to check them needs to be designed into the chip earlier than they're made.
“What we're doing now's taking all of these learnings and automating the answer, making it out there common objective for everyone to make use of,” Gupta advised Reuters.
He mentioned making the testing course of simpler for chips with superior packaging, additionally known as 2.5 and three-dimensional packaging, will assist give the brand new know-how a lift.
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